Topaz

ASIC designers increasingly want to combine their proprietary, differentiating logic with standard technology blocks (such as processors, system buses, memory controllers, encryption engines, etc.) from their SoC supplier’s IP portfolio.

By following this design approach, ASIC designers can focus on their differentiating logic, their "secret sauce", with the resulting benefit of getting their ASIC done faster and with fewer engineering resources.

Addressing this need, K-micro designed and fabricated a computing subsystem which includes the MIPS32® 24Kf™ processor, the Sonics SiliconBackplane™ and Sonics3220™ SMART Interconnects™, the SafeNet® SafeXcel™ security engine, an off-chip industry-standard Open Core Protocol (OCP) interface, and numerous other blocks including on-chip SRAM, a Flash-memory controller, a DMA interface, an Interrupt controller, and a Timer.

Unlike structured ASICs, which use pre-defined "slices", Topaz-based SoCs are designed and fabricated by K-micro using a standard cell flow, giving our customers the smallest possible die size and unit price and highest possible performance for their Topaz-based SoCs. The Topaz-based design approach is idea for high-volume applications needing computing, including PON ONU/OLT, set-top boxes, printers, routers, and storage devices.

Figure 1: Topaz Architecture
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Figure 2: Topaz Development Board, Feature Topaz 0.13µm Chip

ASIC designers can add-in their user logic to Topaz as is:

Figure 3: Topaz Plus Customer Logic
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Or, they can customize Topaz by easily adding and/or removing IP blocks. For example, for a PON application, ASIC designers could replace the Serial and OCP interfaces in Topaz with K-micro Burst-Mode CDR and 10/100 PHY & MAC.

To enable the simple insertion or deletion of blocks from Topaz, K-micro has developed OCP interfaces for most blocks in its IP portfolio, including:

• Fast-Lock CDR for PON
• IEEE 802.11
• PCI Express
• SATA
• ARM processors
• MPEG-4
• Image processing
• USB 2.0
• 10G SerDes with Adaptive Receive Equalization
• 6G CEI SerDes
• Etc.

Topaz Development System
The Topaz chip on the Topaz development board does not have any customer logic in it. So, how would a customer validate their logic with Topaz?

The answer is that they would put their logic into a FPGA development board and then connect that board to the Topaz board (the OCP interface on Topaz is used to connect to an external device, such as an FPGA). Once they validate the combination of their logic plus Topaz, they would work with K-micro to combine Topaz and their customer logic in a single SoC.

Figure 4: FPGA Development Board for Topaz

Figure 5: Topaz + FPGA Development Boards

For even greater capability, the Topaz + FPGA development boards can be joined with an ATX motherboard. The ATX board adds additional functionality, such as 10/100 Ethernet connection, PCI slots, etc.

Figure 6: Topaz + FPGA + ATX Boards

• ARM
• Ethernet MAC PHY
• MIPS
• PCI Express
• SATA
• Security Engine
• SERDES
• Sonics SMX S3220
• USB

• Printers
• Networking devices
• External storage devices
• Mice and other peripherals
• Wireless keyboards
• PDAs
• Desktops
• Mobile phones
• Gaming
• Security Cameras