This is the high-speed serial transfer core Generation 1 serial ATA host controller IP, designed exclusively for ASICs based on the Serial ATA 1.0a Specification.

It consists of Physical (PHY), Link, Transport, and Command layers, and achieves high-speed transfer using a 1.5-Gbps differential signal. It uses the AHB bus interface and DMA for the user interface, and transmits data via the Command layer.

Basic Specification:

• Serial transfer using a 1.5-Gbps differential signal
• Supports SSC (Speed Spectrum Clocking) (from -5,000 ppm to 0 ppm).
• Internal 100-Ω resistance for termination
• Out Of Bands (OOB) signal generation and detection
• 8B/10B encoding/decoding
• Scrambling/descrambling using LFSR
• 32-bit CRC generation and check
• Legacy ATA-compatible register set
• Supports the Maser only mode
• The Command layer register address can be changed
• Low power consumption
• Supports a maximum of four Serial ATA channels

• ARM
• MIPS
• CPU
• USB

• Storage Devices
• RAID controllers
• Printers