This is an ASIC-dedicated IP that supports Endpoint devices and is compatible with PCI Express Base Specification Revision 1.1 issued by PCI SIG.

This IP consists of PHY, LINK, TRANSACTION, and bus interface layers, and achieves high-speed transfer using a 2.5-Gbps differential signal. It uses an AHB bus for the bus interface, the Slave mode for read/write operations, and the Master mode for transferring a large volume of data.

Basic Specification:

• Compatible with PCI Express Base Specification Revision 1.1
• Serial transfer using a 2.5-Gbps differential signal
• Symbol lock based on detection of the COM symbol
• RX-side lane polarity determination and inversion
• 8B/10B encoding/decoding
• Scrambling/descrambling using LFSR
• Inter-lane skew adjustment and framing when multiple lanes are being used
• Compliance pattern generation
• Automatic generation of Initial FC/Update FC
• Supports a maximum packet size of 4 KB
• Has the following three types of link configuration:
• x1: Uses lane 0
• x2: Uses lanes 0 and 1
• x4: Uses lanes 0, 1, 2, and 3

• ARM
• MIPS
• SATA
• USB

• Printers
• Networking devices
• External storage devices
• Computers