K-micro is the leader in advanced yet affordable ASIC technology.  We are a leading-edge (not bleeding edge) ASIC supplier, offering a broad portfolio of advanced system-level IP at reasonable prices.

Why K-micro For Your ASIC/SoC?

Advanced ASIC technology:

• SerDes, including Patented Adaptive Receive Equalization, CEI 11G/6G & lower-speed SerDes, Fast-lock CDR for PON, PCI Express
• Low-power design techniques, including voltage islands and clock gating
• Broad IP portfolio, including ARM, MIPS, Ceva DSPs, StarCore DSPs, Sonics, SafeNet, Embedded TCAM, SPI4.2, etc.
• Hierarchical design flow for multi-million gate designs
• Advanced testing, including high-speed at-speed and delay fault
• Topaz computing sub-system
  

Affordable:

• Highly efficient manufacturing, focused on core competencies (design center, full-custom IP development, including SerDes, quality and reliability and supply chain management)
• Economies-of-scale via large unit volumes shipped to consumer and LCD display customers (leads to lower costs)

Process Technology

K-micro was a pioneer in the ASIC industry in using foundries.  In 1997 we adopted a fabless business model for advanced process technologies.   The fabless ASIC supplier model is being adopted by many of our competitors today – we have a decade of experience with it!  The benefit to customers of this 10-years of experience include on-time delivery through a smooth supply chain and affordable prices through strong relationships with our fab partners.

K-micro Process Technologies

Product	Geometry (Drawn)	Core Voltage (V)	I/O Voltage (V)	Max. Metal Layers	Gate Density (Kgates/ mm2)	Fab
Standard Cell
K40G K40L	40nm	0.9 GP 1.1 LP	3.3/2.5/1.8	10	1620	TSMC
K65G K65L	65nm	1.0 GP 1.2 LP	3.3/2.5/1.8	9	854	TSMC
KS8500	90nm	1.0*	3.3/2.5	9	457	TSMC
KS7500	0.13μm	1.2	3.3/2.5	8	256	TSMC
KS6500	0.15μm	1.5	3.3	7	180	UMC
KS6000	0.18μm	1.8	3.3	6	94	UMC & He Jian
Gate Array
KG850	90nm	1.0*	3.3/2.5	9	290	TSMC
KG750	0.13μm	1.2	3.3/2.5	8	149	TSMC
KG650	0.15μm	1.5	3.3	1	106	UMC

* Supports Voltage Islands

Higher Density Libraries Than Our Competitors
Process technology is just one part of the story – libraries are the other part.  K-micro’s 7-grid libraries provide higher gate densities than those of competitors:

ASIC Supplier	0.13µm Standard Cell Library Density (Kgates/mm2)	Source
K-micro	256	K-micro
IBM	175  (K-micro is 46% denser)	Source Link
ST	200  (K-micro is 28% denser)	Source Link

Virage Logic is the source for K-micro’s 7-grid libraries.  K-micro helped Virage develop their 7-grid ASAP Logic Ultra-High Density (UHD) libraries.  By compacting cells into a 7-high grid, K-micro libraries are able to achieve higher gate densities than 8-grid (or higher) libraries used by competitors.  The benefit to customers of our higher density libraries is lower unit costs.

K-micro “Rainbow Wafer”
Another important differentiation between K-micro and some other fables ASIC suppliers is the process we follow to validate the design of physical IP (such as SerDes, PLLs, etc.) before allowing it to be used by our customers.  K-micro uses “Rainbow Wafers” to ensure that any physical IP in our IP portfolio will work over the entire valid process spectrum:

Figure 1: K-micro Rainbow Wafer

Design Flow

The K-micro Team: It’s Not the Tools, It’s How They’re Used
Of all aspects of an ASIC project, design flow places the heaviest demands on a customer’s design engineers and requires the closest teamwork between the customer and provider. Consequently, the design flow provides the best opportunity to distinguish K-micro from its competitors and for customers to enjoy the most conspicuous benefits. For example, while all providers use standard electronic design automation (EDA) tools, the real challenge lies in using these tools to create a flow that is smooth and efficient from the customer’s perspective. For example, each process technology has idiosyncrasies that affect design implementation, and only experienced ASIC design center engineers understand how to use their EDA tools to obtain optimal results and minimize demands upon customers.

Flat Design Flow
K-micro uses a traditional flat-design flow for low-to-medium-density designs. In a flat-design flow, the customer creates a netlist and K-micro places and routes it. Key tasks and the tools used to complete those tasks are shown below.

Figure 1: Overview of K-micro Flat Design Flow

 

Task Tools Kick-Off Meeting N/A Synthesis (gate-level) Synopsys (Design Compiler) JTAG BSR insertion/memory BIST insertion K-micro tools Scan Insertion/Trial ATPG • Scan: Synopsys (DFT Compiler) • ATPG: Synopsys (TetraMAX), Cadence/IBM (TestBench) Initial Floorplanning Cadence (First Encounter) = Customer = K-micro = Both

Figure 2: Key Tasks and Tools For The Technology Optimization Phase

 

Task Tools LDRC (Logical DRC) Synopsys (DC Ultra, Design Compiler), K-micro tools Fault Grading (if necessary) Cadence (Verifaoult-XL) Formal Verification Synopsys (Design VERIFYer, Formality), Verplex (Tuxedo-LEC) Static Timing Analysis Synopsis (Prime Time) (Customer Sign-Off) Gate-Level Simulation Mentor (ModelSim), Cadence (VerilogXL, NC-Verilog), Synopsys (VCS); Cadence Products are golden simulators for K-micro (Customer Sign-Off) Poer Estimating (if necessary) Synopsys (Power Compiler) = Customer = K-micro = Both

Figure 3: Key Tasks and Tools Used for the Design Verification Phase

 

Task Tools Floor Planning Cadence (First Encounter) Power Analysis Synplicity (Fortify RealPower, Fortify Power Planner) Clock Tree Synthesis Cadence (CTGen, First Enconter) Place & Route Cadence (Silicon Ensemble DSM, First Encounter + NanoRoute Ultra) Interconnect RC Analysis Synopsis (Star-RCXT) Noise Analysis Sequence (Physical Studio) ATE Rule Check K-micro tools DRC & LVS Mentor (Calibre) Static Timing Analysis Synopsis (Prime Time) (Customer Sign-Off) Test Program Generation K-micro tools = Customer = K-micro = Both

Figure 4: Key Tasks and Tools Used for the Layout Phase

 

Hierarchical Design Flow
K-micro uses a hierarchical design flow for high-density designs, eliminating dozens of iterations and leading to faster timing closure. Customer service is even more important for hierarchical design flows, for it requires extremely close cooperation and earlier engagement between the customer and K-micro. New tasks in the hierarchical flow include hands-on design partitioning, where designs are broken into blocks according to guidelines based on functionality, size balancing of partitions, and timing budget allocation for the partitions. K-micro invested more than 2-years of effort to develop its hierarchical design flow and acquired multiple licenses for existing tools and new tools.

 

Figure 5: Overview of K-micro Hierarchical Design Flow

 

Figure 6: Block-Level Partitioning by K-micro and the Customer

 

Figure 7: K-micro Hierarchical Design Flow Details

Intellectual Property

By using IP from K-micro’s extensive IP portfolio, customers can complete their ASIC designs faster, enabling their product to get to market faster.

K-micro’s corporate strategy is to focus on our core competencies and work with partners for other items.   A core competency for K-micro is developing physical IP, such as SerDes, PLLs, CDRs, ADCs, DACs, etc.   Key features of K-micro’s physical IP include:

• VHDL/Verilog models for simulation during design.
  
• K-micro test chips to prove the designs in silicon.
  
• Guaranteed (fixed) timing in hard layout when necessary.
  
• Static timing analysis support to verify performance.
  
• High fault coverage by means of pre-generated test vectors

Digital IP, which can easily be synthesized to target any ASIC technology, is readily available from a wide variety of sources today.  The digital IP in K-micro’s IP portfolio is acquired from established, well-known partners such as ARM, MIPS, CEVA, StarCore, Mentor, etc.

Figure 1: K-micro IP Strategy

K-micro IP Partners Program
Unfortunately, a key obstacle to the proliferation of third-party digital IP is the negotiation of license agreements, which can take more time to complete than the technical evaluation of the IP, delaying the ASIC’s project schedule in the process. 
 
To simplify the usage of third-party digital IP, K-micro has negotiated license agreements with selected third-party IP suppliers, its “IP Partners”.  Customers who select IP from K-micro’s IP Partners can be assured that K-micro can quickly acquire the IP on their behalf, speeding their ASIC’s time-to-market.  K-micro’s IP Partners include ARM, MIPS, CEVA, Mentor Graphics, Mysticom, SafeNet, and Sonics.

Advanced Packaging Technology

In many modern ASICs, the design of the package is as important as the design of the ASIC itself.  K-micro has extensive packaging experience, including:

• High-performance, flip-chip BGAs with ball counts in excess of 2000 balls,
  
• Multi-chip modules (MCMs) – multiple die in a single package
  
• Multi-package modules (MPMs) – multiple packaged devices put together in a single package

Stacked BGAs

K-micro designs BGA redistribution layers (RDLs) and BGA substrates itself, ensuring the final packaged device performs as expected.   Design techniques we employ in RDL and substrate design include:

• Using substrate routing to overcome RDL trace length differences
  
• Specifying tolerances for substrate routing – example, Bus[31:0] to be within 1 mm of each other
  
• Using zig-zag routing to match lengths between different signals

 

Figure 1: K-micro RDL Routing

 

Figure 2: K-micro Substrate Routing

 

Figure 3:  K-micro MPM

 

Figure 4:  K-micro Stacked BGA

Testing

K-micro’s ASIC testing methodology includes full scan insertion, memory BIST insertion, and Iddq testing. In addition to performing final high-speed testing, K-micro also supports JTAG boundary scan register (BSR) insertion. Our state-of-the-art test center has dozens of test machines – including state-of-the-art Advantest and HP testers.

Scan
To help identify manufacturing defects, K-micro is able to insert scan chains into the ASIC as a service to our customers. To minimize the effects of scan insertion on performance, we provide customers with pre-scan libraries that incorporate the effects of scan insertion on performance and die area. K-micro also uses proprietary tools to prevent scan chain shift errors. We create vectors from the scan chain, which we use to test the ASIC before shipment to customers. K-micro’s scan insertion techniques ensure very high fault coverage.

BIST
K-micro uses BIST to test its memories for manufacturing defects. Our controller adds minimal overhead (about 1,000 gates) and a single controller supports dozens of memory blocks. Multiple controllers can be instantiated into hierarchical designs.

Iddq Testing
K-micro uses advanced Iddq testing to help identify manufacturing defects in its ASICs. We use automatic address selection techniques to measure thousands of addresses. We also utilize fast DC measurement techniques to conduct Iddq testing in a quick and cost effective manner.

JTAG (IEEE 1149.1 compatible)
K-micro’s JTAG support includes providing customers with the Test Access Port Controller, and BSDL files.

Embedded Memory

ASIC Memories
In response to the demand for high-performance embedded memory, K-micro offers a range of options that can be embedded into any ASIC – each delivering the efficiency that only on-chip memory provides. These options – which include single-port and dual-port SRAM, DRAM, and ROM (some with high-speed and write per bit and byte options) – are available for any application, and they are available in a variety of sizes, configurations, access times, and cycle times.

K-micro CAM Macro Solutions: Low Power, High Performance, Small Size
K-micro’s in-house content-addressable memory (CAM) ASIC macro solutions, based on our highly successfully ASSP CAM products, are proven technologies that offer the key advantages of low power consumption, high performance, and small die size. They are available for 0.18μ process technology today, with 0.13μ planned. K-micro’s CAM ASIC macro supports both ternary-mode and binary-mode operation. In particular, the 0.18μ CAM macro has the following features:

• Supports ternary and binary mode operation
   
• Two-port architecture
   
• Two configurable banks
   
• High-speed search and deterministic latency
   
• Effective command set
   
• Patented low-power match detector