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KAWASAKI ANNOUNCES MATRIX ASIC STRATEGIC INITIATIVE
Signs Comprehensive, Multi-Million Dollar ASIC Library Licensing Agreement with Virage Logic as Key First Step in Initiative
SAN JOSE, Calif. — March 15, 2004 — Kawasaki Microelectronics today announced its Matrix ASIC strategic initiative to allow customers to mix and match libraries with different transistor heights, different transistor voltage thresholds, and different architectures in a single ASIC device. Kawasaki launched this initiative to lessen the impacts of increased transistor leakage currents and mask costs associated with advanced process technologies. Target applications include platform ASICs, ASICs for implementing emerging standards, and ASICs with ASSP-agnostic interfaces.
ASIC vendors generally limit customers to the use of only a single library, although some ASIC vendors allow designers to use multiple voltage threshold (Vt) libraries in a single chip. Kawasaki’s initiative adds two more dimensions, different transistor heights (also known as grid sizes) and different architectures, creating an extensive matrix of libraries that can be mixed and matched in a single ASIC device.
For example, a designer developing an ASIC for a network access application could use:
- A shorter transistor height, standard Vt, standard cell library for nominal-performance user logic,
- A taller transistor height, low Vt standard cell library for a high-performance CPU core,
- A low Vt memory library for a high-performance CPU data cache,
- A standard Vt memory library for nominal-performance user memory, and
- A shorter transistor height, standard Vt gate array library for user logic that can easily be changed to create derivatives.
By using multiple transistor height libraries, Matrix ASICs have smaller die sizes, lower costs, and lower leakage currents versus ASICs that use only a single transistor height library. By mixing standard cell and gate array architectures, Matrix ASICs lower the NRE costs associated with making derivative chips. Kawasaki expects to accept ASIC designs under this initiative in the second half of 2004.
As a key first step in this initiative, Kawasaki announced that it has signed a comprehensive, multi-million dollar agreement with Virage Logic Corporation (Nasdaq:VIRL), a leading provider of best-in-class semiconductor IP platforms. Under the terms of this agreement, Kawasaki gains access to Virage Logic’s ASAP Logic product line with its patented architecture and routing methodology.
"Virage Logic, with its excellent technology, broad selection and superior customer support, was our first choice when considering library partners to help us realize our vision", said Hisaya Keida, General Manager, Product Marketing and Development Dept. of Kawasaki. "Our development focus now is to work with our EDA partners, such as Cadence, to create a design flow that can easily combine all these libraries together in a single ASIC."
"Kawasaki’s innovative initiative will provide significant benefits for designers of advanced technology ASICs", said Jim Ensell, vice president of marketing for Virage Logic. "As part of its initiative, Kawasaki helped us develop our ASAP Logic Ultra-High-Density (UHD) standard cell library. The ASAP Logic UHD library provides up to a 30% improvement in logic area and up to 20% lower power consumption compared to conventional standard cell products."
"We have been working closely with Kawasaki for a number of years on developing advanced ASIC design flows", said Wei-Jin Dai, platform vice president, digital IC implementation, Cadence Design Systems, Inc. "We look forward to working with them to establish a design flow to support their initiative, bringing the advantages of Matrix ASICs, including lower costs, lower leakage currents, and lower NREs for derivatives, to a broad range of customers."
About Kawasaki Microelectronics
Kawasaki Microelectronics is the leader in advanced yet affordable ASIC semiconductor technology solutions. The company’s innovative core technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking, wireless, and electronic-storage markets. The company is an active participant in industry standards organizations, including the Network Processing Forum (NPF), Optical Internetworking Forum (OIF), PCI Special Interest Group (PCI-SIG), USB Implementers Forum, MPEG Industry Forum (MPEGIF), Mobile Computing Promotion Consortium (MCPC), the Bluetooth Special Interest Group, and the Digital Display Working Group (DDWG). Kawasaki has design centers in Boston, Osaka, San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit its English-language web site at http://www.klsi.com/, its Japanese-language web site at http://www.k-micro.com/, or e-mail to info@k-micro.com.
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Press Contact:
Sacha Arts (for Kawasaki Microelectronics)
Slider & Associates
408-356-3099
sacha@sliderassociates.com
Virage Logic
Sabina Burns
Virage Logic Corporation
510-743-8115
sabina.burns@viragelogic.com
or
Kerry McClenahan
McClenahan Bruer Communications
503-546-1002
kerry@mcbru.com
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release other than statements of historical fact are forward-looking statements, including, for example, statements relating to Virage Logic's business outlook, new products and new relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to maintain and develop new relationships with third-party foundries, adoption of technologies by semiconductor companies and increases in the demand for their products, the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies, the company's ability to obtain royalty revenues from customers in addition to license fees, business and economic conditions generally and in the semiconductor industry in particular, competition in the market for embedded memories and other risks including those described in the Company's Annual Report on Form 10-K for the period ended September 30, 2002, filed with the Securities and Exchange Commission (SEC) on December 16, 2002, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic or from the SEC's website (www.sec.gov), and in press releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
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