K-micro :: About K-micro

About K-micro

About K-micro
K-micro at a Glance
Employment

K-micro’s innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets.

The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, Bangalore, and Tokyo.

K-micro at a Glance

Date Founded	1990
Worldwide Revenues	>$500M
Employees	>650
President & CEO	Yukio Yamauchi
Corporate Headquarters	Makuhari, Japan (greater Tokyo metropolitan area)
Quick Overview	Only major ASIC supplier focused solely on ASICs An ASIC industry pioneer in using foundries Value Proposition: Advanced Yet Affordable ASIC Technology™
Notable Milestones	1990: Founded as a division of Kawasaki Steel 1997: Decided to adopt the fables ASIC supplier business model; established relationship with Chartered 1999: Added UMC as a foundry 2001: K-micro spun-off from Kawasaki Steel, becoming an independent company 2002: Added TSMC as a foundry 2003: Added Chinese foundry He Jian 2004: Adopted consistent worldwide name and brand and expanded into Europe 2005: Released the Topaz Development system 2006: India Branch opened 2008 Released the CatsEye Development system
Design Centers	Bangalore, San Jose, Taipei, Tel Aviv, Tokyo
Why K-micro ASIC?	Advanced ASIC Technology Advanced ASIC Technology: SerDes, including Patented Adaptive Receive Equalization, CEI 11G/6G & lower-speed SerDes, Fast-lock CDR for PON, PCI Express Low-power design techniques, including voltage islands and clock gating Broad IP portfolio, including ARM, MIPS, Ceva DSPs, StarCore DSPs, Sonics, SafeNet, Embedded TCAM, SPI4.2 Hierarchical design flow for multi-million gate designs Advanced testing, including high-speed at-speed and delay fault Topaz computing sub-system Affordable: Highly efficient manufacturing, focused on core competencies Economies-of-scale via large unit volumes shipped to consumer and LCD display customers
K-micro’s Strategic Plan	Focus on core competencies and work with partners for other items. By doing so, we believe we are more competitive and nimble than our all-in-one, vertically integrated competitors. Our core competencies are: ASIC design center Physical IP development, including SerDes Quality & Reliability Supply chain management
Other	K-micro’s North American subsidiary previously was known as Kawasaki LSI USA, Inc. or KLSI. In the summer of 2004, the North American subsidiary was renamed Kawasaki Microelectronics America, Inc. (or K-micro America) in order for the company to have a consistent brand name worldwide.

Employment

K-micro welcomes inquiries from qualified candidates. If you are interested in being part of a corporate culture that emphasizes professional challenges, a team effort, and a customer-oriented focus based on open client communications, adherence to schedules, and product excellence, you are in the right place! Contact jobs@k-micro.us.

Available Positions:

» Design Engineer

Design Engineer

Responsibility:

Perform application specific integrated circuit ("ASIC") design and development including coding in Verilog/VHDL & simulation.
Perform digital logic design & synthesis & static timing closure (“STA”), add design for testability ("DFT") logic and simulation to test vectors and verification.

Education:

Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Science or related engineering field.

Experience:

One (1) year experience in the job offered or as a design engineer, electrical engineer or related researching or teaching role.

Special Requirements :

Experience or coursework with: high-speed digital VLSI design; RTL verilog, low power design and ability to write meaningful test benches; perform simulation validation and timing verification; Any suitable combination of education, training or experience is acceptable.

Location: San Jose, California

To apply submit resume and credentials to the attention of Li Chou, Kawasaki Microelectronics America Inc., 2550 N. First Street, Suite 500, San Jose, CA 95131 or email to Ms. Chou's attention at lchou@k-micro.us

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